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num icro ? nuc1 22 data s heet arm cortex? - m0 32- bit microcontroller may 16 , 201 4 page 1 of 65 revision 1.09 numicro ? family nuc1 2 2 data s heet the information described in this document is the exclusive intellectual property of nuvoton technology corporation and shall not be reproduced without permission from nuvoton. nuvoton is providing this document only for reference purposes of numicro tm microcontroller based system design. nuvoton assumes no responsibility for errors or omissions. all data and specifications are subject to change without notice. for additional information or questions, please contact: nuvoton technology corporation. www.nuvoton.com
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 2 of 65 revision 1.09 table of contents list of f igures .................................................................................................................................. 4 list of tables .................................................................................................................................... 5 1 general description ......................................................................................................... 6 2 features ................................................................................................................................. 7 2.1 numicro ? nuc12 2 features ........................................................................................... 7 3 parts information li st and pin configura tion .................................................... 10 3.1 numicro ? nuc122 products selection guide .............................................................. 10 3.2 numicro ? nuc122 pin diagram ................................................................................... 11 3.2.1 numicro ? nuc122 lqfp 64 - pin .................................................................................... 11 3.2.2 numicro ? nuc122 lqfp 48 - pin .................................................................................... 12 3.2.3 numicro ? nuc122 qfn 33 - pin ...................................................................................... 13 3.3 numicro ? nuc122 pin description .............................................................................. 14 3.3.1 numicro ? nuc122 pin description for lqfp64/lqfp48/qfn3 3 .................................. 14 4 block diagram .................................................................................................................... 18 4.1 numicro ? nuc122 block diagram ............................................................................... 18 5 functional descripti on .................................................................................................. 19 5.1 arm ? cortex? - m0 core ............................................................................................... 19 5.2 system manager ........................................................................................................... 21 5.2.1 overview ........................................................................................................................ 21 5.2.2 system reset ................................................................................................................. 21 5.2.3 system power distribution ............................................................................................. 22 5.2.4 system timer (systick) ................................................................................................. 23 5.2.5 nested vectored interrupt controller (nvic) .................................................................. 24 5.3 clock controller ............................................................................................................ 28 5.3.1 overview ........................................................................................................................ 28 5.3.2 clock generator ............................................................................................................. 29 5.3.3 system clock & systick clock ....................................................................................... 30 5.3.4 peripherals clock ........................................................................................................... 31 5.3.5 power down mode clock ............................................................................................... 31 5.4 usb device controller (usb) ....................................................................................... 32 5.4.1 overview ........................................................................................................................ 32 5.4.2 features ......................................................................................................................... 32 5.5 general purpose i/o (gpio) ........................................................................................ 33 5.5.1 overview and features .................................................................................................. 33 5.5.2 function description ....................................................................................................... 3 3 5.6 i 2 c serial interface controller (master/slave) (i 2 c) ...................................................... 35 5.6.1 overview ........................................................................................................................ 35 5.7 pwm generator and capture timer (pwm) ................................................................ 37 5.7.1 overview ........................................................................................................................ 37 5.7.2 features ......................................................................................................................... 38 5.8 real time clock (rtc) ................................................................................................. 39
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 3 of 65 revision 1.09 5.8.1 overview ........................................................................................................................ 39 5.8.2 features ......................................................................................................................... 39 5.9 serial peripheral interface (spi) ................................................................................... 40 5.9.1 overview ........................................................................................................................ 40 5.9.2 features ......................................................................................................................... 40 5.10 timer controller (tmr) ................................................................................................. 41 5.10.1 overview ...................................................................................................................... 41 5.10.2 featu res ....................................................................................................................... 41 5.11 watchdog timer (wdt) ................................................................................................ 42 5.11.1 features ....................................................................................................................... 43 5.12 uart interface controller (uart) ............................................................................... 44 5.12.1 overview ...................................................................................................................... 44 5.12.2 features ....................................................................................................................... 46 5.13 ps/2 device controller (ps2d) ..................................................................................... 47 5.13.1 overview ...................................................................................................................... 47 5.13.2 features ....................................................................................................................... 47 6 flash memory control ler (fmc) ................................................................................ 48 6.1 overview ....................................................................................................................... 48 6.2 features ........................................................................................................................ 48 7 electrical character istics ......................................................................................... 49 7.1 absolute maximum ratings .......................................................................................... 49 7.2 dc electrical characteristics ........................................................................................ 50 7.2.1 numicro ? nuc122 dc electrical characteristics ........................................................... 50 7.3 ac electrical characteristics ........................................................................................ 54 7.3.1 external 4~24 mhz high speed crystal ac electrical characteristics ........................... 54 7.3.2 external 4~24 mhz high speed crystal ......................................................................... 54 7.3.3 external 32.768 khz low speed crystal ........................................................................ 55 7.3.4 internal 22.1184 mhz high speed oscillator .................................................................. 55 7.3.5 internal 10 khz low speed oscillator ............................................................................ 55 7.4 analog characteristics .................................................................................................. 56 7.4.1 specification of ldo & power management .................................................................. 56 7.4.2 specification of low voltage reset ................................................................................ 57 7.4.3 specification of brownout detector ................................................................................ 57 7.4.4 specification of power - on reset (5 v) ........................................................................... 57 7.4.5 specification of usb phy .............................................................................................. 58 7.5 spi dynamic characteristics ........................................................................................ 59 7.5.1 dynamic characteristics of data input and output pin ................................................... 59 8 package dimensions ......................................................................................................... 61 8.1 64l lqfp (7x7x1.4mm footprint 2.0 mm) .................................................................... 61 8.2 48l lqfp (7x7x1.4mm footprint 2.0mm) ..................................................................... 62 8.3 33l qfn (5x5x0.8mm) ................................................................................................. 63 9 re vision history ................................................................................................................ 64
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 4 of 65 revision 1.09 list of f igures figure 5 - 1 functional controller diagram ...................................................................................... 19 figure 5 - 2 numicro ? nuc122 power distribution diagram ........................................................... 22 figure 5 - 3 clock generator global view diagram ......................................................................... 28 figure 5 - 4 clock generator block diagram ................................................................................... 29 figure 5 - 5 system clock block diagram ....................................................................................... 30 figure 5 - 6 systick clock control block diagram .......................................................................... 30 figure 5 - 7 push - pull output ........................................................................................................... 33 figure 5 - 8 open - drain output ....................................................................................................... 34 figure 5 - 9 quasi - bidirectional i/o mode ........................................................................................ 34 figure 5 - 10 i 2 c bus timing ............................................................................................................ 35 figure 5 - 11 timing of interrupt and reset signal s ........................................................................ 43 figure 7 - 1 typical crystal application circuit ................................................................................ 54 figure 7 - 2 spi master mode timing .............................................................................................. 59 figure 7 - 3 spi slave mode timing ................................................................................................ 60
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 5 of 65 revision 1.09 list of tables table 1 - 1 connectivity supported table .......................................................................................... 6 table 5 - 1 exception model ............................................................................................................ 25 ta ble 5 - 2 system interrupt map ..................................................................................................... 26 table 5 - 3 vector table format ...................................................................................................... 27 table 5 - 4 watchdog timer time - out interval selection ................................................................ 42 table 5 - 5 uart baud rate equation ............................................................................................ 44 table 5 - 6 uart baud rate setting table ..................................................................................... 45
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 6 of 65 revision 1.09 1 general description the numicro ? nuc1 22 series are 32 - bit microcontrollers with cortex? - m0 core runs up to 6 0 mhz, up to 32k/64k - byte embedded flash, 4k/8k - byte embedded sram, and 4k - byte loader rom for the in system program ( isp ) function . it also integrates timers, watchdog timer, rtc, uart, spi, i 2 c, pwm timer, gpio, usb 2.0 f ull s peed device, low voltage res et controller and brownout detector. product line uart spi i 2 c usb ps/ 2 nuc122 y y y y y table 1 - 1 connectivity supported table
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 7 of 65 revision 1.09 2 features 2.1 numicro ? nuc1 2 2 features ? core C arm ? cortex? - m0 core runs up to 6 0 mhz C one 24 - bit system timer C support low power sleep mode C single - cycle 32 - bit hardware multiplier C nvic for the 32 interrupt inputs, each with 4 - levels of priority C serial wire debug supports with 2 watchpoints/4 breakpoints ? wide operating voltage ranges from 2.5 v to 5.5 v ? flash memory C 32k/64k bytes flash for program code C 4kb f lash for isp loader C support in s ystem p rogram (isp) function to update a p p lication code C 512 byte s page erase for f lash C 4kb d ata f lash C support 2 wire in circuit program ( icp ) function to update code through swd/ ice interface C support fast parallel programming mode by external programmer ? sram memory C 4k/8k bytes embedded sram ? clock control C flexible selection fr om different clock sources C buil t - in 22.1184 mhz high speed osc for system operation ? trimmed to 1 % at +25 and v dd = 3.3 v ? trimmed to 5 % at - 40 ~ +85 and v dd = 2.5 v ~ 5.5 v C built - in 10 khz low speed osc for w atchdog timer and w ake - up operation C support one pll, up to 6 0 mhz, for high performance system operation C external 4~24 mhz high speed crystal input for usb and precise timing operation C external 32.768 khz low speed crystal input for rtc function and low power system operation ? gpio C four i/o modes: ? quasi bi - direction ? push - pull output ? open - drain output ? input only with high impendence C ttl/schmitt trigger input selectable C i/o pin can be configured as interrupt source with edge/level setting C high driver and high sink io mode support ? timers C 4 sets of 32- bit timers with 24- bit counters and one 8 - bit prescaler C counter auto reload
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 8 of 65 revision 1.09 ? watch d og timer C multiple clock sources C 8 selectable time - out period from 1. 6 ms ~ 26.0 sec (depends on clock source) C wdt can wake - up from power down or idle mode C interrupt or reset selectable while w atchdog timer time - out ? rtc C support software compensation by setting frequency compensate register (fcr) C support rtc counter (second, minute, hour) and calendar counter (day, month, year) C support alarm registers (second, minute, hour, day, month, year) C 12- hour or 24 - hour mode C automatic leap year recognition C support time tick interrupt C support wake - up function ? pwm /capture C built - in up to two 16 - bit pwm generators provide four pwm outputs or two complementary paired pwm outputs C each pwm generator equi pped with one clock source selector, one clock divider, one 8 - bit prescaler and one dead - zone generator for complementary paired pwm C up to four 16- bit digital capture timers (shared with pwm timers) provide four rising/falling capture inputs C support captur e interrupt ? uart C two uart controller s C uart ports with flow control (tx d , rx d , cts and rts) C uart ports with 16 - byte fifo for standard device C support irda (sir) function C support rs - 485 9 - bit mode and direction control C programmable baud - rate generator up to 1/16 system clock ? spi C up to two sets of spi device C master up to 2 5 mhz , and slave up to 1 2 mhz (chip is working @ 5 v) C support spi master/slave mode C full duplex synchronous serial data transfer C variable length of transfer data from 1 to 32 bits C msb or lsb first data transfer C 2 slave/device select lines when it is as the master, and 1 slave/device select line when it is as the slave C byte suspend mode in 32 - bit transmission
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 9 of 65 revision 1.09 ? i 2 c C one set of i 2 c device C master/slave mode C bidirectional data transfer between maste rs and slaves C multi - master bus (no central master) C arbitration between simultaneously transmitting masters without corruption of serial data on the bus C serial clock synchronization allows devices with different bit rates to communicate via one serial bus C s erial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer C programmable clocks allow versatile rate control C i 2 c - bus controller support s multiple address recognition (four slave address with mask option) ? usb 2.0 f ull - speed device C one set of usb 2.0 fs device 12mbps C on - chip usb transceiver C provide 1 interrupt source with 4 interrupt events C support control, bulk in/out, interrupt and isochronous transfers C auto suspend function when no bus signaling for 3 ms C provide 6 programmable endpoints C include 512 b ytes internal sram as usb buffer C provide remote wake - up capability ? brown out d etector C with 4 levels: 4.5 v/3.8 v/2.7 v/2.2 v C support brownout interrupt and reset option s ? one built - in ldo ? low voltage reset ? operating temperature: - 40 ~ 85 ? packages: C all green package (rohs) C lqfp 64 - pin (7mmx7mm) C lqfp 48 - pin C qfn 3 3 - pin
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 10 of 65 revision 1.09 3 parts information li st and pin configuratio n 3.1 numicro ? nuc1 2 2 products selection guide part number flash (kb) isp rom (kb) sram (kb) i/o timer connectivity i 2 s comp. pwm adc rtc isp icp package uart spi i 2 c usb lin ps / 2 nuc1 22z d2an 64 kb 4kb 8 kb up to 18 4x32 - bit 1 2 1 1 - - - - - - - v qfn3 3 nuc1 22z c1an 32 kb 4kb 4 kb up to 18 4x32 - bit 1 2 1 1 - - - - - - - v qfn3 3 nuc1 22 ld2an 64 kb 4kb 8 kb up to 30 4x32 - bit 2 2 1 1 - 1 - - 4 - v v lqfp48 nuc1 22 lc1an 32 kb 4kb 4 kb up to 30 4x32 - bit 2 2 1 1 - 1 - - 4 - v v lqfp48 nuc1 22s d2an 64 kb 4kb 8 kb up to 41 4x32 - bit 2 2 1 1 - 1 - - 4 - v v lqfp 64 nuc1 22s c1an 32 kb 4kb 4 kb up to 41 4x32 - bit 2 2 1 1 - 1 - - 4 - v v lqfp 64
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 11 of 65 revision 1.09 3.2 numicro ? nuc1 2 2 pin diagram 3.2.1 numicro ? nuc1 22 lqfp 64- pin nuc122 lqfp 64-pin 38 37 40 39 41 64 32 36 30 29 28 27 26 25 34 35 31 33 20 21 18 19 16 17 14 15 13 22 23 24 1 2 3 4 6 7 8 9 10 5 11 12 ice_dat ice_ck pc.9/spiclk1 pc.11/mosi10 pc.8/spiss10 pc.13 pc.10/miso10 pc.12 pa.13/pwm1 pa.15/pwm3 pa.12/pwm0 pa.14/pwm2 txd1/pb.5 ldo vss vdd cts1/pb.7 rts1/pb.6 rxd1/pb.4 i2c1sda/pa.10 x32i i2c1scl/pa.11 pvss x32o d+ pc.4 pc.5 pc.3/mosi00 pc.0/spiss00 pc.2/miso00 pc.1/spiclk0 d- vdd33 vbus pb.10/spiss01/tm2 pb.9/spiss11/tm1 pd.5 ps2dat/pf.2 pd.1 pd.2 pd.3 pd.4 ps2clk/pf.3 pd.0 xt1_out xt1_in /reset int0/pb.14 tm0/pb.8 pd.8 pd.10 pd.11 pd.9 pb.0/rxd0 pb3/cts0 pb.2/rts0 pb.1/txd0 vss 42 44 43 46 45 47 vdd 48 vss avdd int1/pb.15 vss vdd 50 52 49 51 53 54 55 56 57 58 59 60 61 62 63 figure 3 - 1 numicro ? nuc1 22 lqfp 64- pin pin diagram
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 12 of 65 revision 1.09 3.2.2 numicro ? nuc1 22 lqfp 48 - pin avdd pd.0 pd.1 pvss x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 rts1/pb.6 cts1/pb.7 ldo vdd vss pd.3 pd.4 pd.5 xt1_out xt1_in /reset ice_ck ice_dat pc.10/miso10 pc.11/mosi10 pc.12 pc.13 pd.2 ps2dat/pf.2 pb.9/spiss11/tm1 pb.10/spiss01/tm2 pb.1/txd0 pb.0/rxd0 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 nuc122 lqfp 48-pin pc.0/spiss00 pc.1/spiclk0 pc.2/miso00 pc.3/mosi00 rxd1/pb.4 txd1/pb.5 vdd33 vbus d+ d- pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3 pc.8/spiss10 pc.9/spiclk1 ps2clk/pf.3 figure 3 - 2 numicro ? nuc1 22 lqfp 48 - pin pin diagram
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 13 of 65 revision 1.09 3.2.3 numicro ? nuc1 2 2 qfn 3 3 - pin avdd spiss01/pd.1 int0/pb.14 i2c1scl/pa.11 i2c1sda/pa.10 ldo vdd vss pd.3 xt1_out xt1_in /reset pvss ice_ck ice_dat pc.10/miso10 pc.11/mosi10 pc.12 pc.13 pd.2 10 11 12 13 14 15 16 33 vss 32 31 30 29 28 8 7 6 5 4 3 2 1 19 20 21 22 23 24 pc.0/spiss00 pc.1/spiclk0 pc.2/miso00 pc.3/mosi00 spiss11/rxd1/pb.4 txd1/pb.5 vdd33 vbus d+ d- pc.8/spiss10 pc.9/spiclk1 nuc122 qfn 33-pin 9 17 18 27 26 25 figure 3 - 3 numicro ? nuc1 22 qfn 3 3 - pin pin diagram
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 14 of 65 revision 1.09 3.3 numicro ? nuc1 2 2 pin description 3.3.1 numicro ? nuc1 22 pin description for lqfp 64/lqfp48/qfn33 pin no. pin name pin type description lqfp 64 lqfp 48 qf n 33 1 1 pb.14 i/o general purpose input/output digital pin / int0 i /int0: external interrupt1 input pin 2 2 x32o o 32.768 khz low speed crystal output pin 3 3 x32i i 32.768 khz low speed crystal input pin 4 4 2 pa.11 i/o general purpose input/output digital pin i2c1scl i/o i2c 1 scl: i 2 c 1 clock pin 5 5 3 pa.10 i/o general purpose input/output digital pin i2c1sda i/o i2c 1 sda: i 2 c 1 data input/output pin 6 p d.8 i/o general purpose input/output digital pin 7 p d.9 i/o general purpose input/output digital pin 8 p d.10 i/o general purpose input/output digital pin 9 p d.11 i/o general purpose input/output digital pin 10 6 4 pb.4 i/o general purpose input/output digital pin rxd1 i rxd1: data receiver input pin for uart1 spiss 11 i/o spiss 11 : spi1 slave select pin (for qfn33 only) 11 7 5 pb.5 i/o general purpose input/output digital pin txd1 o txd1: data transmitter output pin for uart1 12 8 pb.6 i/o general purpose input/output digital pin rts1 o rts1: request to send output pin for uart1 13 9 pb.7 i/o general purpose input/output digital pin cts1 i cts1: clear to send input pin for uart1 14 10 6 ldo p ldo output pin 15 11 7 vdd p power supply for i/o ports and ldo source for internal pll and digital function 16 12 8 vss p ground 17 13 9 vbus p power supply: from usb host or hub. 18 14 10 vdd33 p internal power regulator output 3.3 v decoupling pin
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 15 of 65 revision 1.09 pin no. pin name pin type description lqfp 64 lqfp 48 qf n 33 19 15 11 d - usb usb differential signal d - 20 16 12 d+ usb usb differential signal d+ 21 17 pb.0 i/o general purpose input/output digital pin rx d 0 i rx d 0: data receiver input pin for uart0 22 18 pb.1 i/o general purpose input/output digital pin tx d 0 o tx d 0: data transmitter output pin for uart0 23 pb.2 i/o general purpose input/output digital pin rts0 o rts0: request to send output pin for uart0 24 pb.3 i/o general purpose input/output digital pin cts0 i cts0: clear to send input pin for uart0 25 pc.5 i/o general purpose input/output digital pin 26 pc.4 i/o general purpose input/output digital pin 27 19 13 pc.3 i/o general purpose input/output digital pin mosi 00 o mosi 00: spi 0 mosi (master out, slave in) pin 28 20 14 pc.2 i/o general purpose input/output digital pin miso 00 i miso 00: spi 0 miso (master in, slave out) pin 29 21 15 pc.1 i/o general purpose input/output digital pin spi clk0 i/o spiclk0: spi0 s erial clock pin 30 22 16 pc.0 i/o general purpose input/output digital pin spiss 00 i/o spiss 00 : spi0 slave select pin 31 23 pb.10 i/o general purpose input/output digital pin tm2 o tm2: timer2 external counter input spiss 01 i/o spiss01: spi0 2 nd slave select pin 32 24 pb.9 i/o general purpose input/output digital pin tm1 o tm1: timer1 external counter input spiss 11 i/o spiss 1 1: spi1 2 nd slave select pin 33 vss p ground 34 25 17 pc.13 i/o general purpose input/output digital pin 35 26 18 pc.12 i/o general purpose input/output digital pin
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 16 of 65 revision 1.09 pin no. pin name pin type description lqfp 64 lqfp 48 qf n 33 36 27 19 pc.11 i/o general purpose input/output digital pin mosi 10 o mosi 10: spi 1 mosi (master out, slave in) pin 37 28 20 pc.10 i/o general purpose input/output digital pin miso 10 i miso 10: spi 1 miso (master in, slave out) pin 38 vdd p power supply for i/o ports 39 29 21 pc.9 i/o general purpose input/output digital pin spi clk1 i/o spiclk1: spi1 s erial clock pin 40 30 22 pc.8 i/o general purpose input/output digital pin spiss 10 i/o spiss 10 : spi1 slave select pin 41 31 pa.15 i/o general purpose input/output digital pin pwm3 o pwm 3: pwm output pin 42 vss p ground 43 32 pa.14 i/o general purpose input/output digital pin pwm2 o pwm 2: pwm output pin 44 33 pa.13 i/o general purpose input/output digital pin pwm1 o pwm 1: pwm output pin 45 34 pa.12 i/o general purpose input/output digital pin pwm0 o pwm 0: pwm output pin 46 35 23 ice _ dat i/o serial wired debu g ger data pin 47 36 24 ice_ck i serial wired debu g ger clock pin 48 37 25 avdd ap p ower supply for internal analog circuit 49 38 pd.0 i/o general purpose input/output digital pin 50 39 26 pd.1 i/o general purpose input/output digital pin spiss 01 i/o spiss 01 : spi0 2 nd slave select pin (for qfn33 only) 51 40 27 pd.2 i/o general purpose input/output digital pin 52 41 28 pd.3 i/o general purpose input/output digital pin 53 42 pd.4 i/o general purpose input/output digital pin 54 43 pd.5 i/o general purpose input/output digital pin 55 pb.15 i/o general purpose input/output digital pin
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 17 of 65 revision 1.09 pin no. pin name pin type description lqfp 64 lqfp 48 qf n 33 / int1 i /int1: external interrupt 1 input pin 56 44 29 xt 1 _out o crystal output pin 57 45 30 xt 1 _in i crystal input pin 58 46 31 /reset i external reset input : low active, set this pin low reset chip to initial state . with internal pull - up. 59 33 vss p ground 60 vdd p power supply for i/o ports 61 47 pf . 2 i/o general purpose input/output digital pin ps2dat i/o ps/ 2 d ata pin 62 48 pf . 3 i/o general purpose input/output digital pin ps2clk i/o ps/ 2 clock pin 63 1 32 pvss p pll ground 64 pb.8 i/o general purpose input/output digital pin tm0 o tm0: timer0 external counter input note: pin type i=digital input, o=digital output; ai=analog input; p=power pin; ap=analog power
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 18 of 65 revision 1.09 4 block diagram 4.1 numicro ? nuc1 22 block diagram flash 64 kb cortex-m0 60 mhz clk_ctl isp 4 kb sram 8 kb gpio a,b,c,d ps/2 uart 1 -115k timer 2/3 rtc wdt i 2 c 1 spi 0/1 pwm 0~3 timer 0/1 por brownout lvr p l l ldo 2.5 v~ 5.5 v usb-fs ram 512 b usbphy 10 khz 32.768 khz 22.1184 mhz 4~24 mhz uart 0 -115k figure 4 - 1 numicro ? nuc1 22 block diagram
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 19 of 65 revision 1.09 5 functional d escription 5.1 arm ? cortex? - m0 core the cortex? - m0 processor is a configurable, multistage, 32 - bit r isc processor. it has an amba ah b - lite interface and includes an nvic component. it also has optional hardware debug functionality. the processor can execute thumb code and is compatible with other cortex? - m profile processor. following figure shows the functional controllers of processo r. cortex-m0 processor core nested vectored interrupt controller (nvic) breakpoint and watchpoint unit debugger interface bus matrix debug access port (dap) debug cortex-m0 processor cortex-m0 components wakeup interrupt controller (wic) interrupts serial wire or jtag debug port ahb-lite interface figure 5 - 1 functional controller diagram t he implemented device provides: ? a low gate count processor that features: C the arm ? v6 - m thumb ? instruction set C thumb - 2 technology C arm ? v6 - m compliant 24 - bit systick timer C a 32 - bit hardware multiplier C the system interface suppo rts little - endian data accesses C the ab ility to have deterministic, fi xed - latency, and interrupt handling C load/store - multiples and multicycle - multiplies that can be abandoned and restarted to faci litate rapid interrupt handling C c application binary interface compliant exception model. this is the arm ? v6 - m, c application binary interface (c - abi) compliant exception model that enables the use of pure c functions as in terrupt handlers C low power sleep mode entry using wait for interrupt (wfi), wait for even t (wfe) instructions, or the return from interrupt sleep - on- exit feature ? nvic that features: C 32 external interrupt inputs, each with four levels of priority C dedicated non - maskable interrupt (nmi) input. C support for both level - sensitive and pulse - sensitive interrupt lines C wake - u p interrupt controller (wic), providing ultra - low power sleep mode support.
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 20 of 65 revision 1.09 ? d ebug support C four hardware breakpoints. C two watchpoints. C program counter sampling register (pcsr) for non - intrusive code profiling. C single step and vector catch capabilities. ? bus interfaces: C single 32 - bit amba - 3 ahb - lite system interface that provides simple integration to all system peripherals and memory. C sing le 32 - bit slave port that supports the dap (debug access port) .
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 21 of 65 revision 1.09 5.2 system manager 5.2.1 overview system management includes these following sections: ? system resets ? system memory map ? system management registers for part number id, chip reset and on - chip controllers reset, multi - functional pin control ? system timer (systick) ? nested vectored interrupt controller (nvic) ? system control registers 5.2.2 system reset the system reset can be issued by one of the below listed events . t hese reset event flags can be read from rst s rc register. ? the power - on reset ? the low level on the /reset pin ? watchdog timer time - out reset ? low voltage reset ? brown o ut detect or reset ? cortex? - m0 reset ? system reset both system reset and power - on reset can reset the whole chip including all peripherals. the difference between system reset and power - on reset is external crystal circuit and ispcon . bs bit. system reset doesn?t reset external crystal circuit and ispcon . bs bit, but power - on reset does.
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 22 of 65 revision 1.09 5.2.3 system power distribution in this chip , the power distribution is divided into three segments. ? analog power from avdd and avss provides the power for analog components operation. ? digital power from vdd and vss supplies the power to the internal regulator which pr ovides a fixed 1.8 v power for digital operation and i/o pins. ? usb transceiver power from vbus offers the power for operating the usb transceiver. the outputs of internal voltage regulators, ldo and vdd33, require an external capacitor which should be loc ated close to the corresponding pin. analog power (avdd) should be the same voltage level of the digital power (vdd). the following diagram shows the power distribution of this chip . 5v to 1.8v ldo usb transceiver 5v to 3.3v ldo pll brown out detector por50 por18 low voltage reset rtc 32k osc. flash digital logic 3.3v 1.8v irc 22.1184mhz & 10khz osc. avdd avss vdd vss vbus vdd33 d+ d- ldo 1uf 10uf io cell gpio x32o x32i pvss power distribution figure 5 - 2 numicro ? nuc1 2 2 power distribution diagram
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 23 of 65 revision 1.09 5.2.4 system timer (systick) the cortex? - m0 includes an integrated system timer, systick. systick provides a simple, 24 - bit clear - on- write, decrementing, wrap - on - zero counter with a flexible control mechanism. the counter can be used in several different ways, for example: ? an rtos tick timer which fires at a programmable rate (for example 100hz) and invokes a systick routine. ? a high speed alarm timer using core clock. ? a variable rate alarm or signal timer ? the duration range dependent on the reference clock used and the dynamic range of the counter. ? a simple counter. software can use this to measure time to completion and time used. ? an internal clock source control based on missing/me eting durations. the countflag bit - field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. when enabled, the timer will count down from the value i n the systick current value register (syst_cvr) to zero, and reload (wrap) to the value in the systick reload value register (syst_rvr) on the next clock cycle , then decrement on subsequent clocks. when the counter transitions to zero, the countflag status bit is set. the countflag bit clears on reads. the syst_cvr value is unknown on reset. software should write to the register to clear it to zero before enabling the feature. this ensures the timer will count from the syst_rvr value rather than an arbitrar y value when it is enabled. if the syst_rvr is zero, the timer will be maintained with a current value of zero after it is reloaded with this value. this mechanism can be used to disable the feature independently from the timer enable bit. for more detail ed information, please refer to the documents ?arm ? cortex? - m0 technical reference manual? and ?arm ? v6 - m architecture reference manual?.
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 24 of 65 revision 1.09 5.2.5 nested vectored interrupt controller (nvic) cortex? - m0 provides an interrupt controller as an integral part of the exception mode, named as ?nested vectored interrupt controller (nvic)?. it is closely coupled to the processor kernel and provides following features: ? nested and vectored interrupt support ? automatic processor state saving and restoration ? dynamic priority c hanging ? reduced and deterministic interrupt latency the nvic prioritizes and handles all supported exceptions. all exceptions are handled in ?handler mode?. this nvic architecture supports 32 (irq[31:0]) discrete interrupts with 4 levels of priority. all o f the interrupts and most of the system exceptions can be configured to different priority levels. when an interrupt occurs, the nvic will compare the priority of the new interrupt to the current running one?s priority. if the priority of the new interrupt is higher than the current one, the new interrupt handler will override the current handler. when any interrupts is accepted, the starting address of the interrupt service routine (isr) is fetched from a vector table in memory. there is no need to determi ne which interrupt is accepted and branch to the starting address of the correlated isr by software. while the starting address is fetched, nvic will also automatically save processor state including the registers ?pc, psr, lr, r0~r3, r12? to the stack. at the end of the isr, the nvic will restore the mentioned registers from stack and resume the normal execution. thus it will take less and deterministic time to process the interrupt request. the nvic supports ?tail chaining? which handles back - to - back inte rrupts efficiently without the overhead of states saving and restoration and therefore reduces delay time in switching to pending isr at the end of current isr. the nvic also supports ?late arrival? which improves the efficiency of concurrent isrs. when a higher priority interrupt request occurs before the current isr starts to execute (at the stage of state saving and starting address fetching), the nvic will give priority to the higher one without delay penalty. thus it advances the real - time capability. for more detailed information, please refer to the documents ?arm ? cortex? - m0 technical reference manual? and ?arm ? v6 - m architecture reference manual?.
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 25 of 65 revision 1.09 exception model and system interrupt map 5.2.5.1 the following table lists the exception model supported by n umicro ? nuc1 2 2 . software can set four levels of priority on some of these exceptions as well as on all interrupts. the highest user - configurable priority is denoted as ?0? and the lowest priority is denoted as ?3?. the default priority of all the user - configurable interrupts is ?0?. note that priority ?0? is treated as the fourth priority on the system, after three system exceptions ?reset?, ?nmi? and ?hard fault?. exception name vector number priority reset 1 -3 nmi 2 -2 hard fault 3 -1 reserved 4 ~ 10 reserved svcall 11 configurable reserved 12 ~ 13 reserved pendsv 14 configurable systick 15 configurable interrupt (irq0 ~ irq31) 16 ~ 47 configurable table 5 - 1 exception model vector number interrupt number (bit in interrupt registers) interrupt name source ip interrupt description 0 ~ 15 - - - system exceptions 16 0 bod_out brown o ut brown o ut low voltage detected interrupt 17 1 wdt_int wdt watch d og timer interrupt 18 2 eint0 gpio external signal interrupt from pb.14 pin 19 3 eint1 gpio external signal interrupt from pb.15 pin 20 4 gpab_int gpio external signal interrupt from p a[15:0]/p b[1 3 : 0 ] 21 5 gpcd_int gpio external interrupt from pc [15:0] / pd [15:0] 22 6 pwma_int pwm 0~3 pwm0 , pwm1, pwm2 and pwm 3 interrupt 23 7 reserved reserved reserved 24 8 tmr0_int tmr0 timer 0 interrupt 25 9 tmr1_int tmr1 timer 1 interrupt 26 10 tmr2_int tmr2 timer 2 interrupt 27 11 tmr3_int tmr3 timer 3 interrupt
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 26 of 65 revision 1.09 28 12 reserved reserved reserved 29 13 uart1_int uart1 uart1 interrupt 30 14 spi0_int spi0 spi0 interrupt 31 15 spi1_int spi1 spi1 interrupt 32 16 reserved reserved reserved 33 17 reserved reserved reserved 34 18 reserved reserved reserved 35 19 i2c1_int i 2 c1 i 2 c1 interrupt 36 20 reserved reserved reserved 37 21 reserved reserved reserved 38 22 reserved reserved reserved 39 23 usb_int usbd usb 2.0 fs device interrupt 40 24 ps2_int ps/ 2 ps/ 2 interrupt 41 25 reserved reserved reserved 42 26 reserved reserved reserved 43 27 reserved reserved reserved 44 28 pwrwu_int clkc power down wake - up interrupt 45 29 reserved reserved reserved 46 30 reserved reserved reserved 47 31 rtc_int rtc real t ime c lock interrupt table 5 - 2 system interrupt map
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 27 of 65 revision 1.09 vector table 5.2.5.2 when any interrupts is accepted, the processor will automatically fetch the starting address of the interrupt service routine (isr) from a vector table in memory. for arm ? v6 - m, the vector table base address is fixed at 0x00000000. the vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers. the vector number on previous page defines the order of entries in the vector table associated with ex ception handler entry as illustrated in previous section. vector table word offset description 0 sp_main ? the main stack pointer vector number exception entry pointer using that vector number table 5 - 3 vector table format operation description 5.2.5.3 nvic interrupts can be enabled and disabled by writing to their corresponding interrupt set - enable or interrupt clear - enable register bit - field. the registers use a write - 1 - to - enable and write - 1 - to - clear policy, both registers reading back the current enabled state of the corresponding interrupts. when an interrupt is disabled, interrupt assertion will cause the interrupt to become pending, however, the interrupt will not activate. if an interrupt is active when i t is disabled, it remains in its active state until cleared by reset or an exception return. clearing the enable bit prevents new activations of the associated interrupt. nvic interrupts can be pended/un - pended using a complementary pair of registers to th ose used to enable/disable the interrupts, named the set - pending register and clear - pending register respectively. the registers use a write - 1 - to - enable and write - 1 - to - clear policy, both registers reading back the current pended state of the corresponding interrupts. the clear - pending register has no effect on the execution status of an active interrupt. nvic interrupts are prioritized by updating an 8 - bit field within a 32 - bit register (each register supporting four interrupts). the general registers assoc iated with the nvic are all accessible from a block of memory in the system control space and will be described in next section.
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 28 of 65 revision 1.09 5.3 clock controller 5.3.1 overview the clock controller generates the clock s for the whole chip , includ ing system clocks and all perip heral clocks . the clock controller also implements the power control function with the individually clock on/off control, clock source select ion and clock divider . the chip will not enter power d ow n mode until cpu set s the p ower d own enable bit (pwr_down _en ) and cortex? - m0 core execute s the wfi i nstruction. after that, chip enter s power down mode and wait for wake - up interrupt source triggered to leave power down mode. i n the power down mode, the clock controller turn s off the external 4~24 mhz high speed crystal and internal 22.1184 mhz high speed oscillator to reduce the overall system power consumption. 1 0 pllcon[19] 22.1184 mhz 4~12 mhz pllfout 111 011 010 001 4~24 mhz 32.768 khz 4~24 mhz hclk 22.1184 mhz 000 1/2 1/2 1/2 clksel0[5:3] 1 0 systick tmr 3 uart 0-1 i 2 c 1 spi 0-1 usb rtc ps2 wdt pwm 0-1 pwm 2-3 tmr 0 tmr 1 tmr 2 cpu fmc 32.768 khz 10 khz 111 010 001 000 hclk 32.768 khz 4~24 mhz 111 011 010 001 pllfout 32.768 khz 4~24 mhz 10 khz 22.1184 mhz 000 clksel0[2:0] syst_csr[2] cpuclk 1/(hclk_n+1) pclk cpuclk hclk 11 01 00 pllfout 4~24 mhz 22.1184 mhz clksel1[25:24] 22.1184 mhz clksel1[22:20] clksel1[18:16] clksel1[14:12] clksel1[10:8] 1/(usb_n+1) pllfout 11 10 01 00 hclk 4~24 mhz 22.1184 mhz 32.768 khz clksel1[31:28] 22.1184 mhz 32.768 khz bod 10 khz 11 10 clksel1[1:0] hclk 1/2048 1/(uart_n+1) 22.1184 mhz 4~24 mhz figure 5 - 3 clock g enerator global view diagram
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 29 of 65 revision 1.09 5.3.2 clock generator the clock generator consists of 5 clock sources which are list ed as below: ? one external 32.768 khz low speed crystal ? one external 4~24 mhz high speed crystal ? one programmable pll fout ( pll source consists of external 4~24 mhz high speed crystal and internal 22.1184 mhz high speed oscillator) ? one internal 22.1184 mhz high speed oscillator ? one internal 10 khz low speed oscillator xt_out external 4~24 mhz crystal xtl12m_en (pwrcon[0]) xt_in internal 22.1184 mhz oscillator osc22m_en (pwrcon[2]) 0 1 pll pll_src (pllcon[19]) pll fout x32o external 32.768 khz crystal 32.768 khz xtl32k_en (pwrcon[1]) x32i internal 10 khz oscillator osc10k_en(pwrcon[3]) 4~24 mhz 22.1184 mhz 10 khz figure 5 - 4 clock g enerator b lock d iagram
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 30 of 65 revision 1.09 5.3.3 system clock & systick clock the system clock has 5 clock sources which were generated from clock generator block. the clock source switch depends on the register hclk_ s ( clksel0[2:0]). the block diagram is list ed below. 111 011 010 001 pllfout 32.768 khz 4~24 mhz 10 khz hclk_s (clksel0[2: 0]) 22.1184 mhz 000 1/(hclk_n+1) hclk_n (clkdiv[3:0]) cpu in power down mode cpu ahb apb cpuclk hclk pclk figure 5 - 5 system clock block diagram the clock source of systick in cortex? - m0 core can use cpu clock or external clock (syst_csr[2]). if using external clock, the systick clock (stclk) has 5 clock sources. the clock source switch depends on the setting of the register stclk_s (clksel0[5:3]. the block diagram is listed below. 111 011 010 001 4~24 mhz 32.768 khz 4~24 mhz hclk stclk_s (clksel0[5:3]) stclk 22.1184 mhz 000 1/2 1/2 1/2 figure 5 - 6 systick c lock control block diagram
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 31 of 65 revision 1.09 5.3.4 peripherals clock the peripherals clock had different clock source switch setting which depends on the different peripheral. 5.3.5 power d own m ode clock when chip enters into power down mode, system clocks, some clock sources, and some peripheral clocks will be disabled. some clock sources and peripherals clock are still active in power down mode. t hese clocks which still keep activ ity that are list ed as below: ? clock generator ? internal 10 khz low speed oscillator clock ? external 32.768 khz low speed crystal clock ? peripherals clock ( when wdt adopts 10 khz low speed as clock source and rtc adopts 32.768 khz low speed as clock source )
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 32 of 65 revision 1.09 5.4 usb device controller (usb) 5.4.1 overview there is one set of usb 2.0 full - speed device controller and transceiver in this device . it is compliant with usb 2.0 full - speed device specification and support control/bulk/interrupt/isochronous transfer types. in this device controller, there are two main interfaces: the apb bus and usb bus which comes from the u sb phy transceiver. for the apb bus, the cpu can program control registers through it. there are 512 bytes internal sram as data buffer in this controller. for in or out transfer, it is necessary to write data to sram or read data from sram through the apb interface or sie. users need to set the effective starting address of sram for each endpoint buffer through ?buffer segmentation register (bufsegx)?. there are six endpoints in this controller. each of the endpoint can be configured as in or out endpoint. all the operations including control, bulk, interrupt and isochronous transfer are implemented in this block. the block of endpoint control is also used to manage the data sequential synchronization, endpoint states, current start address, transaction sta tus and data buffer status for each endpoint. there are four different interrupt events in this controller. they are the wake - up function, device plug - in or plug - out event , usb events, like in ack, out ack etc , and bus events, like suspend and resume, etc. any e vent will cause an interrupt, and users just need to check the related event flags in interrupt event status register (usb_intsts) to acknowledge what kind of interrupt occurring, and then check the rela ted usb endpoint status register (usb_epsts) to acknowledge what kind of event occurring in this endpoint . a software - disable function is also support for this usb controller. it is used to simulate the disconnection of this device from the host. if user e nables drv se0 bit (usb_drvse0), the usb controller will force the output of usb_dp and usb_dm to level low and its function is disabled . after disable the drv se0 bit , host will enumerate the usb device again. reference: universal serial bus specification revision 1.1 5.4.2 features this universal serial bus (usb) performs a serial interface with a single connector type for attaching all usb peripherals to the host system. following is the feature list ing of this usb. ? compliant with usb 2.0 full - speed specificat ion ? provide 1 interrupt vector with 4 different interrupt events (wakeup, fldet, usb and bus) ? support control/bulk/interrupt/isochronous transfer type ? support suspend function when no bus activity existing for 3 ms ? provide 6 endpoints for configurable control/bulk/interrupt/isochronous transfer types and maximum 512 bytes buffer size ? provide remote wake - up capability
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 33 of 65 revision 1.09 5.5 general purpose i/o (gpio) 5.5.1 overview and features numicro ? nuc1 2 2 has u p to 41 general purpose i/o pins can be shared with other function pins; it depends on the chip configuration. these 41 pins are arranged in 4 ports named with gpioa, gpiob, gpioc and gpio d . each port equips maximum 16 pins. each one of the 41 pins is independent and has the corresponding register bits to control the pin mode function and data. the i/o type of each of i/o pins can be configured by software individually as input, output, open - drain or quasi - bidirectional mode. after reset, the i/o type of all pins stay in quasi - bidirectional mode and port data register gpiox_dout [15:0] resets to 0x00 0 0_ff ff. each i/o pin equips a very weakly individual pull - up resistor which is about 110k ? ~300k ? for v dd is from 5. 5 v to 2.5 v. 5.5.2 function description input mode explanation 5.5.2.1 set gpiox_pmd (pmdn[1:0]) to 00b the gpiox port [n] pin is in input mode and the i/o pin is in tri - state (high impedance) without output drive capability . the gpiox_pin value reflects the status of the corresponding port pins. output mode explanation 5.5.2.2 set gpiox _pm d ( pmdn[1:0]) to 01b the gpiox port [n] pin is in output mode and the i/o pin supports digital output function with source/sink current capability. the bit value in the corresponding bit [n] of gpio x _dout is driven on the pin. port pin input data port latch data p n vdd figure 5 - 7 push - pull output
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 34 of 65 revision 1.09 open - drain mode explanation 5.5.2.3 set gpiox_pmd (pmdn[1:0]) to 10b the gpiox port [n] pin is in open - drain mode and the digital output function of i/o pin supports only sink current capability, an additional pull - up resister is needed for driving high state. if the bit value in the corresponding bit [n] of gpiox_dout is 0, the pin drive a ?low? output on the pin. if the bit value in the corresponding bit [n] of gpiox_dout is 1, the pin output drives high that is controlled by external pull high resistor. port pin port latch data n input data figure 5 - 8 open - drain output quasi - bidirection al mode explanation 5.5.2.4 set gpiox_pmd (pmdn[1:0]) to 11b the gpiox port [n] pin is in quasi - bidirectional mode and the i/o pin supports digital output and input function at the same time but t he source current is only up to hundreds ua. before the digital input function is performed the corresponding bit in gpiox_dout must be set to 1. the quasi - bidirectional output is common on the 80c51 and most of its derivatives. if the bit value in the cor responding bit [n] of gpiox_dout is 0, the pin drive a ?low? output on the pin. if the bit value in the corresponding bit [n] of gpiox_dout is 1, the pin will check the pin value. if pin value is high, no action takes. if pin state is low, then pin will dr ive strong high with 2 clock cycles on the pin and then disable the strong output drive and then the pin status is control by internal pull - up resistor. note that the source current capability in quasi - bidirectional mode is only about 200 ua to 30 ua for v dd is form 5.0 v to 2.5 v. port pin 2 cpu clock delay input data port latch data p p p n vdd strong very weak weak figure 5 - 9 quasi - bidirectional i/o mode
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 35 of 65 revision 1.09 5.6 i 2 c serial interface controller (master/slave) (i 2 c ) 5.6.1 overview i 2 c is a two - wire, bi - directional serial bus that provides a simple and efficient method of data exchange between devices. the i 2 c standard is a true multi - master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultan eously. data is transferred between a master and a slave synchronously to scl on the sda line on a byte - by - byte basis. each data byte is 8 bits long. there is one scl clock pulse for each data bit with the msb being transmitted first. an acknowledge bit fo llows each transferred byte. each bit is sampled during the high period of scl; therefore, the sda line may be changed only during the low period of scl and must be held stable during the high period of scl. a transition on the sda line while scl is high i s interpreted as a command (start or stop). please refer to the following figure for more detail i 2 c bus timing. t buf stop sda scl start t hd ; sta t low t hd ; dat t high t f t su ; dat repeated start t su ; sta t su ; sto stop t r figure 5 - 10 i 2 c bus timing the device?s on - chip i 2 c logic provides the serial interface that meets the i 2 c bus standard mode specification. the i 2 c port handles byte transfers autonomously. to enable this port, the bit ens1 in i2con should be set to '1'. the i 2 c h/w interfaces to the i 2 c bus via two pins: sda (p a10 , serial data line) and scl (p a11 , serial clock line). pull up resistor is needed for pin p a10 and p a11 for i 2 c operation as these are open drain pins. when the i/o pins are used as i 2 c port, user must set the pins function to i 2 c in advance. the i 2 c b us uses two wires (sda and scl) to transfer information between devices connected to the bus. the main features of the bus are: ? master/slave mode ? bidirectional data transfer between masters and slaves ? multi - master bus (no central master) ? arbitration betwee n simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handshake mechanism to s uspend and resume serial transfer ? built - in a 14 - bit time - out counter will request the i 2 c interrupt if the i 2 c bus hangs up and timer - out counter overflows.
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 36 of 65 revision 1.09 ? external pull - up are needed for high output ? programmable clocks allow versatile rate control ? suppo rts 7 - bit addressing mode ? i 2 c - bus controllers support multiple address recognition ( four slave address with mask option)
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 37 of 65 revision 1.09 5.7 pwm generator and capture timer (pwm) 5.7.1 overview numicro ? nuc1 2 2 only support 1 set of pwm group supports total 2 sets of pwm generators which can be configured as 4 independent pwm outputs, pwm0~pwm3, or as 2 complementary pwm pairs, (pwm0, pwm1) and (pwm2, pwm3) with 2 programmable dead - zone generators. each pwm generator has one 8 - bit prescaler, one clock divider with 5 divide d frequencies (1, 1/2, 1/4, 1/8, 1/16), two pwm timers including two clock selectors, two 16 - bit pwm down - counters for pwm period control, two 16 - bit comparators for pwm duty control and one dead - zone generator. the 4 sets of pwm generators provide eight i ndependent pwm interrupt flags which are set by hardware when the corresponding pwm period down counter reaches zero. each pwm interrupt source with its corresponding enable bit can cause cpu to request pwm interrupt. the pwm generators can be configured a s one - shot mode to produce only one pwm cycle signal or auto - reload mode to output pwm waveform continuously. when pcr.dzen01 is set, pwm0 and pwm1 perform complementary pwm paired function; the paired pwm period, duty and dead - time are determined by pwm0 timer and dead - zone generator 0. similarly, the complementary pwm pairs of (pwm2, pwm3), are controlled by pwm2, timer and dead - zone generator 2 . refer to figures bellowed for the architecture of pwm timers. to prevent pwm driving output pin with unsteady waveform, the 16 - bit period down counter and 16 - bit comparator are implemented with double buffer. when user writes data to counter/comparator buffer registers the updated value will be load into the 16 - bit down counter/ comparator at the time down counter reaching zero. the double buffering feature avoids glitch at pwm outputs. when the 16 - bit period down counter reaches zero, the interrupt request is generated. if pwm - timer is set as auto - reload mode, when the down counter reaches zero, it is reloaded wit h pwm counter register (cnrx) automatically then start decreasing, repeatedly. if the pwm - timer is set as one - shot mode, the down counter will stop and generate one interrupt request when it reaches zero. the value of pwm counter comparator is used for pul se high width modulation. the counter control logic changes the output to high level when down - counter value matches the value of compare register. the alternate feature of the pwm - timer is digital input capture function. if capture function is enabled the pwm output pin is switched as capture input mode. the capture0 and pwm0 share one timer which is included in pwm0 and the capture1 and pwm1 share pwm1 timer, and etc. therefore user must setup the pwm - timer before enable capture feature. after capture fea ture is enabled, the capture always latched pwm - counter to capture rising latch register (crlr) when input channel has a rising transition and latched pwm - counter to capture falling latch register (cflr) when input channel has a falling transition. capture channel 0 interrupt is programmable by setting ccr0.crl_ie0[1] (rising latch interrupt enable) and ccr0.cfl_ie0[2]] (falling latch interrupt enable) to decide the condition of interrupt occur. capture channel 1 has the same feature by setting ccr0.crl_ie1 [17] and ccr0.cfl_ie1[18]. and capture channel 2 to channel 3 on each group have the same feature by setting the corresponding control bits in ccr 2 . for each group, w henever capture issues interrupt 0/1/2/3, the pwm counter 0/1/2/3 will be reload at this m oment. the maximum captured frequency that pwm can capture is confined by the capture interrupt latency. when capture interrupt occurred, software will do at least three steps, they are: read piirx to get interrupt source and read crl r x/cfl r x (x=0~3) to get capture value and finally write 1 to clear piirx to zero . if interrupt latency will take time t0 to finish, the capture signal mustn?t transition during this interval (t0) . in this case, the maximum capture frequency will be 1/t0. for exampl e: hclk = 50 mhz, pwm_clk = 25 mhz, interrupt latency is 900 ns so the maximum capture frequency will is 1/900 ns 1000 k hz
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 38 of 65 revision 1.09 5.7.2 features pwm function features: 5.7.2.1 ? pwm group has two pwm generators. each pwm generator s upports one 8 - bit prescaler, one clock divide r, two pwm - timers (down counter), one dead - zone generator and two pwm outputs. ? up to 16 bits resolution ? pwm interrupt request synchronized with pwm period ? one - shot or auto - reload mode pwm ? up to 1 pwm group to support 4 pwm channels or 2 pwm paired channels capture function features: 5.7.2.2 ? timing control logic shared with pwm generators ? 4 capture input channels shared with 4 pwm output channels ? each channel supports one rising latch register (crlr), one falling latch register (cflr) and capt ure interrupt flag (capifx)
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 39 of 65 revision 1.09 5.8 real time clock (rtc) 5.8.1 overview real time clock (rtc) controller provides user the real time and calendar message. the clock source of rtc is from an external 32.768 khz low speed crystal connected at pins x32i and x32o (reference to pin descriptions) or from an external 32.768 khz low speed oscillator output fed at pin x32i. the rtc controller provides the time message (second, minute, hour) in time loading register (tlr) as well a s calendar message (day, month, year) in calendar loading register (clr). the data message is expressed in bcd format. it also offers alarm function that user can preset the alarm time in time alarm register (tar) and alarm calendar in calendar alarm regis ter (car). the rtc controller supports periodic time tick and alarm match interrupts. the periodic interrupt has 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second which are selected by ttr (ttr[2:0]). when rtc counter in tlr and clr is e qual to alarm setting time registers tar and car, the alarm interrupt flag (riir.aif) is set and the alarm interrupt is requested if the alarm interrupt is enabled (rier.aier=1). both rtc time tick and alarm match can cause chip be w o ke n - up from power down mode if wake - up function is enabled (twke (ttr[3])=1). 5.8.2 features ? there is a time counter (second, minute, hour) and calendar counter (day, month, year) for user to check the time ? alarm register (second, minute, hour, day, month, year) ? 12- hour or 24 - hour m ode is selectable ? leap year compensation automatically ? day of week counter ? frequency compensate register (fcr) ? all time and calendar message is expressed in bcd code ? support periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1 /4, 1/2 and 1 second ? support rtc time tick and alarm match interrupt ? support wake - up chip from power down mode
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 40 of 65 revision 1.09 5.9 serial peripheral interface (spi) 5.9.1 overview the serial peripheral interface ( spi ) is a synchronous serial data communication protocol which operates in full duplex mode. devices communicate in master/slave mode with 4 - wire bi - direction interface. the numicro ? nuc1 2 2 contain s up to two sets of spi controller perform ing a serial - to - para llel conversion on data received from a peripheral device , and a parallel - to - serial conversion on data transmitted to a peripheral device . each set of spi controller can be set as a master that can drive up to 2 external peripheral slave devices; i t also can be configured as a slave device controlled by an off - chip master device. this controller also supports a variable serial clock for special application. 5.9.2 features ? up to two sets of spi controller for numicro ? nuc1 2 2 ? support master or slave mode operation ? support 1 - bit transfer mode ? configurable bit length up to 32 bits of a transfer word and configurable word numbers up to 2 of a transaction , so the maximum bit length is 64 bits for each data trans fer ? provide burst mode operation, transmit/receiv e can be transferred up to two times word transaction in one transfer ? support msb or lsb first transfer ? 2 device/slave select lines in master mode, but 1 device/slave select line in slave mode ? support byte re order in data register ? support b yte or word s usp end m ode ? variable output serial clock frequency in master mode ? support two programmable serial clock frequencies in master mode ? support fifo mode
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 41 of 65 revision 1.09 5.10 timer controller (tmr) 5.10.1 overview the timer controller includes four 32- bit timers , timer0~timer3, which allow s user to easily implement a timer control for applicat i ons . the timer can perform functions like frequency measurement, event counting, interval measurement, clock generation, delay timing, and so on. the timer can generate s an interrupt signal upon timeo ut, or provide the current value during operation. 5.10.2 features ? 4 sets of 32 - bit timers with 24 - bit up - timer and one 8 - bit pre - scale counter ? independent clock source for each timer ? provides one - shot, periodic, toggle and continuous counting operation modes ? time out period = (period of timer clock input) * (8 - bit pre - scale counter + 1) * (24 - bit tcmp) ? maximum counting cycle time = (1 / t mhz) * (2 8 ) * (2 24 ), t is the period of timer clock ? 24- bit timer value is readable through tdr (timer data register) ? suppor t event counting function to count the event from external pin
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 42 of 65 revision 1.09 5.11 watchdog timer (wdt) the purpose of watch d og timer is to perform a system reset when system runs into an unknown state. this prevents system from hanging for an infinite period of time. besides, this watch d og timer supports another function to wake - up chip from power down mode. the w atch d og t imer includes a n 18- bit free running counter with programmable time - out intervals. table 5 - 4 show the w atchdog timer time - out interval selection and figure 5 - 1 1 shows the timing of w atchdog interrupt signal and reset signal. setting wte (wdtcr [7]) enables the watchdog timer and the wdt counter starts counting up. when the counter reaches the selected time - out interval, watchdog timer interrupt flag wt if will be set immediately to request a wdt interrupt if the watchdog timer interrupt enable bit wtie is set, in the meanwhile, a specified delay time (1024 * t wdt ) follows the time - out event. user must set wtr (wdtcr [0]) (watchdog timer reset) high to re set the 18 - bit wdt counter to avoid chip from watchdog timer reset before the delay time expires. wtr bit is cleared automatically by hardware after wdt counter is reset. there are eight time - out intervals with specific delay time which are selected by wat chdog timer interval select bits wtis (wdtcr [10:8]). if the wdt counter has not been cleared after the specific delay time expires, the watchdog timer will set watchdog timer reset flag (wtrf) high and reset chip . this reset will last 63 wdt clocks (t rst ) then chip restarts executing program from reset vector (0x0000_0000). wtrf will not be cleared by w atchdog reset. user may poll wt r f by software to recognize the reset source. wdt also provides wake - up function. when chip is powered down and the watchdog timer wake - up function enable bit (wdtr[4]) is set, if the wdt counter reaches the specific time interval defined by wtis (wdtcr [10:8]) , the chip is w ok en- up from power down state. first example, if wtis is set as 000, the specific time interval for chip to be w o ke n - up from power down state is 2 4 * t wdt . when power down command is set by software, then, chip enters power down state. after 2 4 * t wdt time is elapsed, chip is w o ken - up from power down state. second example, if wtis (wdtcr [1 0:8]) is set as 111, the specific time interval for chip to be w o ke n - up from power down state is 2 18 * t wdt . if power down command is set by software, then, chip enters power down state. after 2 18 * t wdt time is elapsed, chip is wo ken - up from power down state. notice if wtre ( wdtcr [1 ]) is set to 1, after chip is w o ken - up, software should clear the watchdog timer counter by setting wtr( wdtcr [0]) to 1 as soon as possible. otherwise, if the watchdog timer counter is not cleared by setting wtr ( wdtcr [0]) t o 1 before time starting from waking up to software clearing watchdog timer counter is over 1024 * t wdt , the chip is reset by watchdog timer . wtis time - out interval selection t tis interrupt period t int wtr time - out interval (wdt_clk=1 0 k hz) min. t wtr ~ max. t wtr 000 2 4 * t wdt 1024 * t wdt 1.6 ms ~ 104 ms 001 2 6 * t wdt 1024 * t wdt 6.4 ms ~ 108.8 ms 010 2 8 * t wdt 1024 * t wdt 25.6 ms ~ 128 ms 011 2 10 * t wdt 1024 * t wdt 102.4 ms ~ 204.8 ms 100 2 12 * t wdt 1024 * t wdt 409.6 ms ~ 512 ms 101 2 14 * t wdt 1024 * t wdt 1.6384 s ~ 1.7408 s 110 2 16 * t wdt 1024 * t wdt 6.5536 s ~ 6.656 s 111 2 18 * t wdt 1024 * t wdt 26.2144 s ~ 26.3168 s table 5 - 4 watchdog timer time - out interval selection
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 43 of 65 revision 1.09 t tis rst int 1024 * t wdt 63 * t wdt minimum t wtr t int t rst maximum t wtr t wdt ? t wdt : watchdog engine clock time period ? t tis : watchdog timeout interval selection period ? t int : watchdog interrupt period ? t rst : watchdog reset period ? t wtr : watchdog timeout interval period figure 5 - 11 timing of interrupt and reset signal s 5.11.1 features ? 18- bit free running counter to avoid chip from watchdog t imer reset before the delay time expires. ? selectable time - out interval (2^4 ~ 2^18) and the time - out interval is 104 ms ~ 26.3168 s (if wdt_clk = 1 0 k hz). ? reset period = (1 / 1 0 k hz) * 63, if wdt_clk = 1 0 k hz.
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 44 of 65 revision 1.09 5.12 uart interface controller (uart) numicro ? nuc1 2 2 provide s two channel s of universal asynchronous receiver/transmitters (uart 0/ 1 ). both of uart 0 and uart 1 perform normal speed uart, besides, uart 0 and uart 1 also support flow control function. 5.12.1 overview the universal asynchronous receiver/transmitter (uart 0/ 1 ) performs a serial - to - parallel conversion on data received from the periph eral, and a parallel - to - serial conversion on data transmitted from the cpu. the uart controller a lso supports irda sir function and rs - 485 mode functions. each uart channel supports seven types of interrupts including transmitter fifo empty interrupt (int_ thre), receiver threshold level reaching interrupt (int_rda), line status interrupt (parity error or framing error or break interrupt) (int_rls), receiver buffer time - out interrupt (int_tout), modem/wake - u p status interrupt (int_modem), buffer error interr upt (int_buf_err). interrupt number 13 (vector number is 29) supports uart 0/ 1 interrupt. refer to nested vectored interrupt controller chapter f or system interrupt map. t he uart 0/ 1 are equipped 16 - byte transmitter fifo ( tx _fifo) and 16 - byte receiver fifo (rx_fifo). the cpu can read the status of the uart at any time during the operation. the reported status information includes the type and condition of the transfer operations being performed by the uart, as well as 4 error conditions (parity error, framing error, break interrupt and buffer error) probably occur while receiving data. the uart includes a programmable baud rate generator that is capable of dividing clock input by divisors to produce the serial clock that trans mitter and receiver need. the baud rate equation is baud rate = uart_clk / m * [brd + 2], where m and brd are defined in baud rate divider register (ua_baud) . below t able lists the equations in the various conditions and the uart baud rate setting table. mode div_x_en div_x_one divider x brd baud rate equation 0 0 0 b a uart_clk / [16 * (a+2)] 1 1 0 b a uart_clk / [(b+1) * (a+2)] , b must >= 8 2 1 1 don?t care a uart_clk / (a+2), a must >=3 table 5 - 5 uart baud rate equation system clock = 22.1184 mhz high speed baud rate mode0 mode1 mode2 921600 x a=0,b=11 a=22 460800 a=1 a=1,b=15 a=2,b=11 a=46 230400 a=4 a=4,b=15 a=6,b=11 a=94 115200 a=10 a=10,b=15 a=14,b=11 a=190 57600 a=22 a=22,b=15 a=30,b=11 a=382
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 45 of 65 revision 1.09 38400 a=34 a=62,b=8 a=46,b=11 a=34,b=15 a=574 19200 a=70 a=126,b=8 a=94,b=11 a=70,b=15 a=1150 9600 a=142 a=254,b=8 a=190,b=11 a=142,b=15 a=2302 4800 a=286 a=510,b=8 a=382,b=11 a=286,b=15 a=4606 table 5 - 6 uart baud rate setting table the uart 0/ 1 controllers support auto - flow control function that uses two low - level signals, /cts (clear - to - send) and /rts (request - to - send), to control the flow of data transfer between the uart and external devices (ex: modem). when auto - flow is enabled, the uart is not allowed to receive data until the uart asserts /rts to external device. when the number of bytes in the rx fifo equals the value of rts_tri_lev (ua_fcr [19:16]), the /rts is de - as serted. the uart sends data out when uart controller detects /cts is asserted from external device. if a valid asserted /cts is not detected the uart controller will not send data out. the uart controllers also provides serial irda (sir, serial infrared) f unction (user must set irda_en (ua_fun_sel [1]) to enable irda function). the sir specification defines a short - range infrared asynchronous serial transmission mode with one start bit, 8 data bits, and 1 stop bit. the maximum data rate is 115.2 kbps (half duplex). the irda sir block contains an irda sir protocol encoder/decoder. the irda sir protocol is half - duplex only. so it cannot transmit and receive data at the same time. the irda sir physical layer specifies a minimum 10 ms transfer delay between tran smission and reception. this delay feature must be implemented by software. for numicro ? nuc1 2 2 , another alternate function of uart controllers is rs - 485 9 - bit mode function, and direction control provided by rts pin or can program gpio ( pb. 2 for rts0 and pb . 6 for rts1) to implement the function by software. the rs - 485 mode is selected by setting the ua_fun_sel register to select rs - 485 function. the rs - 485 driver control is implemented using the rts control signal from an asynchronous serial port to enabl e the rs - 485 driver. in rs - 485 mode, many characteristics of the rx and tx are same as uart.
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 46 of 65 revision 1.09 5.12.2 features ? full duplex, asynchronous communications ? separate receive / transmit 16 bytes entry fifo for data payloads ? support hardware auto flow control/flow contr ol function (cts, rts) and programmable rts flow control trigger level ? programmable receiver buffer trigger level ? support programmable baud - rate generator for each channel individually ? support cts wake - up function ? support 8 bit s receiver buffer time - out detection function ? programmable transmitting data delay time between the last stop and the next start bit by setting ua_tor [dly] register ? support break error, frame error, parity error and receive / transmit buffer overflow detect function ? fully programma ble serial - interface characteristics ? programmable number of data bit, 5, 6, 7, 8 bit s character ? programmable parity bit, even, odd, no parity or stick parity bit generation and detection ? programmable stop bit, 1, 1.5, or 2 stop bit s generation ? support irda sir function mode ? support for 3/16 bit s duration for normal mode ? support rs - 485 function mode. ? support rs - 485 9 - bit mode ? support hardware or software direct enable control provided by rts pin
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 47 of 65 revision 1.09 5.13 ps/ 2 device controller (ps2d) 5.13.1 overview ps/2 device controller provides basic timing control for ps/2 communication. all communication between the device and the host is managed through the clk and data pins. unlike ps/2 keyboard or mouse device controller, the received/transmit code need s to be translated as meaning ful code by firmware. the device controller generates the clk signal after receiving a request to send, but host has ultimate control over communication. data sent from the host to the device is read on the rising edge and data sent from device to the host is change after rising edge. a 16 bytes fifo is used to reduce cpu intervention. s/ w can select 1 to 16 bytes for a continuous transmission. 5.13.2 features ? host communication inhibit and request to send detection ? reception frame error detection ? programmable 1 to 16 bytes transmit buffer to reduce cpu intervention ? double buffer for data reception ? s/w overrid e bus
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 48 of 65 revision 1.09 6 flash memory controller (fmc) 6.1 overview numicro ? nuc12 2 equips with 64/32 k bytes on chip embedded flash for application program memory (aprom) that can be updated through isp procedure. in system programming (isp) function enables user to update program memory when chip is soldered on pcb. after chip power on , cortex ? - m0 cpu fet ches code from aprom or ldrom decided by boot select (cbs) in config0. by the way, numicro ? nuc122 also provide s additional data flash for user, to store some application dependent data before chip power off . for 64k/32k bytes aprom device, the data flash is fixed at 4k bytes . 6.2 features ? run up to 6 0 mhz with zero wait state for continuous address read access ? 64/32 k b application program memory (aprom) ? 4 k b in system programming (isp) loader program memory (ldrom) ? f ixed 4 k b data flash with 512 bytes page erase unit ? in system program (isp) to update on chip flash
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 49 of 65 revision 1.09 7 electrical character istics 7.1 absolute maximum ratings symbol parameter min . max . unit dc power supply vdd ? vss - 0.3 +7.0 v input voltage vin vss- 0.3 vdd+0.3 v oscillator frequency 1/t clcl 4 24 mhz operating temperature ta -40 +85 c storage temperature tst -55 +150 c maximum current into vdd - 120 ma maximum current out of vss 120 ma maximum current sunk by a i/o pin 35 ma maximum current sourced by a i/o pin 35 ma maximum current sunk by total i/o pins 100 ma maximum current sourced by total i/o pins 100 ma note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliabilit y of the device.
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 50 of 65 revision 1.09 7.2 dc electrical characteristics 7.2.1 numicro ? nuc122 dc electrical characteristics (v dd - v ss =3.3 v, ta = 25 c, fosc = 6 0 mhz unless otherwise specified.) parameter sym. specification test conditions min. typ. max. unit operation voltage v dd 2.5 5.5 v v dd =2.5 v ~ 5.5 v up to 6 0 mhz ldo output voltage v ldo 1.6 1.8 2.1 v v dd R 2. 5 v analog operating voltage av dd 0 v dd v operating current normal run mode @ 6 0 mhz i dd1 2 6 ma v dd = 5.5 v @ 6 0 mhz, enable all ip and pll, xtal=12 mhz i dd2 21 ma v dd = 5.5 v @ 6 0 mhz, dis able all ip and enable pll, xtal=12 mhz i dd3 24 ma v dd = 3 .3 v @ 6 0 mhz, en able all ip and pll, xtal=12 mhz i dd4 19 ma v dd = 3 .3 v @ 6 0 mhz, disable all ip and enable pll, xtal=12 mhz operating current normal run mode @ 12 mhz i dd5 6 .5 ma v dd = 5.5 v @ 12 mhz, enable all ip and disable pll, xtal=12 mhz i dd6 5 ma v dd = 5.5 v @ 12 mhz, dis able all ip and pll, xtal=12 mhz i dd7 4.5 ma v dd = 3 .3 v @ 12 mhz, en able all ip and disable pll, xtal=12 mhz i dd8 3.5 ma v dd = 3 .3 v @ 12 mhz, dis able all ip and pll, xtal=12 mhz operating current normal run mode @ 4 mhz i dd9 3. 5 ma v dd = 5.5 v @ 4 mhz, enable all ip and disable pll, xtal= 4 mhz i dd10 3 ma v dd = 5.5 v @ 4 mhz,
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 51 of 65 revision 1.09 parameter sym. specification test conditions min. typ. max. unit dis able all ip and pll, xtal= 4 mhz i dd1 1 3 ma v dd = 3 .3 v @ 4 mhz, enable all ip and disable pll, xtal=4 mhz i dd1 2 2 ma v dd = 3 .3 v @ 4 mhz, disable all ip and pll, xtal=4 mhz operating current idle mode @ 6 0 mhz i idle 1 17 ma v dd = 5.5 v @ 6 0 mhz, enable all ip and pll, xtal=12 mhz i idle2 12 ma v dd = 5.5 v @ 6 0 mhz, dis able all ip and enable pll, xtal=12 mhz i idle 3 15 ma v dd = 3 .3 v @ 6 0 mhz, enable all ip and pll, xtal=12 mhz i idle 4 11 ma v dd = 3 .3 v @ 6 0 mhz, disable all ip and enable pll, xtal=12 mhz operating current idle mode @ 12 mhz i i d le5 4. 5 ma v dd = 5.5 v @ 12 mhz, enable all ip and disable pll, xtal=12 mhz i i d le6 3. 5 ma v dd = 5.5 v @ 12 mhz, dis able all ip and pll, xtal=12 mhz i idle 7 3 ma v dd = 3 .3 v @ 12 mhz, enable all ip and disable pll, xtal=12 mhz i idle 8 2 ma v dd = 3 .3 v @ 12 mhz, disable all ip and pll, xtal=12 mhz operating current idle mode @ 4 mhz i idle9 3 ma v dd = 5.5 v @ 4 mhz, enable all ip and disable pll, xtal= 4 mhz i i d le10 2. 5 ma v dd = 5.5 v @ 4 mhz, dis able all ip and pll, xtal= 4 mhz i idle 11 2 ma v dd = 3 .3 v @ 4 mhz, enable all ip and disable pll, xtal=4 mhz i idl e12 1 ma v dd = 3 .3 v @ 4 mhz, disable all ip and pll, xtal=4 mhz
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 52 of 65 revision 1.09 parameter sym. specification test conditions min. typ. max. unit standby current power d own mode i pwd1 13 a v dd = 5.5 v, rtc off, no load @ disable bov function i pwd 2 12 a v dd = 3. 3 v, rtc off, no load @ disable bov function i pwd 3 1 5 a v dd = 5. 5 v, rtc run , no load @ disable bov function i pwd 4 1 3 a v dd = 3. 3 v, rtc run , no load @ disable bov function input current pa, pb, pc, pd (quasi - bidirectional mode) i in1 -6 0 - +15 a v dd = 5.5 v, v in = 0 v or v in =v dd input current at /reset [1] i in2 -55 -45 -30 a v dd = 3.3 v, v in = 0.45 v input leakage current pa, pb, pc, pd i lk -2 - + 2 a v dd = 5.5 v, 0 num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 53 of 65 revision 1.09 parameter sym. specification test conditions min. typ. max. unit sink current pa, pb, pc, pd(quasi - bidirectional and push - pull mode) i sk1 10 1 7 20 ma v dd = 4.5 v, v s = 0.45 v i sk1 7 10 13 ma v dd = 2.7 v, v s = 0.45 v i sk1 6 9 12 ma v dd = 2.5 v, v s = 0.45 v brownout voltage with bov_vl [1:0] =00b v bo2. 2 2. 1 2. 2 2. 3 v brownout voltage with bov_vl [1:0] =01b v bo2. 7 2.6 2.7 2.8 v brownout voltage with bov_vl [1:0] =10b v bo3.8 3. 6 3. 75 3.9 v brownout voltage with bov_vl [1:0] =11b v bo4.5 4. 2 4. 4 4. 6 v hysteresis range of bod voltage v b h 30 - 1 5 0 mv v dd = 2.5 v ~ 5.5 v note: 1. /reset pin is a schmitt trigger input. 2. crystal input is a cmos input. 3. pins of pa, pb, pc and pd can source a transition current when they are being externally driven from 1 to 0. in the condition of v dd =5.5 v, t he transitio n current reaches its maximum value when v in approximates to 2 v.
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 54 of 65 revision 1.09 7.3 ac electrical characteristics 7.3.1 external 4~24 mhz high speed crystal ac electrical characteristics t clcl t clcx t chcx t clch t chcl note: duty cycle is 50 %. symbol parameter condition min. typ. max. unit t chcx clock high time 20 - - ns t clcx clock low time 20 - - ns t clch clock rise time - - 10 ns t chcl clock fall time - - 10 ns 7.3.2 external 4~24 mhz high speed crystal parameter condition min. typ. max. unit input clock frequency external crystal 4 12 24 mhz temperature - -40 - 85 typical crystal application circuits 7.3.2.1 crystal c1 c2 r 4 mhz ~ 24 mhz without without without xtal 2 xtal 1 c 1 c 2 r figure 7 - 1 typical crystal application circuit
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 55 of 65 revision 1.09 7.3.3 external 32.768 khz low speed crystal parameter condition min. typ. max. unit input clock frequency external crystal - 32 .768 - khz temperature - -40 - 85 7.3.4 internal 22.1184 mhz high speed oscillator parameter condition min. typ. max. unit center frequency - - 22.1184 - mhz calibrated internal oscillator frequency +25 ; v dd = 3.3 v -1 - +1 % -40 ~ +85 ; v dd = 2.5 v ~ 5.5 v -5 - + 5 % 7.3.5 internal 10 khz l ow s peed oscillator parameter condition min. typ. max. unit center frequency - - 10 - khz calibrated internal oscillator frequency +25 ; v dd = 5 v -30 - +30 % -40 ~ +85 ; v dd = 2.5 v ~ 5.5 v -50 - +50 %
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 56 of 65 revision 1.09 7.4 analog characteristics 7.4.1 specification of ldo & power management parameter min . typ . max . unit note input voltage 2. 5 5 5.5 v v dd input voltage output voltage 1.6 1.8 2.1 v v dd 2. 5 v temperature -40 25 85 quiescent current (pd=0) - 100 - a quiescent current (pd=1) - 5 - a iload (pd=0) - - 100 m a iload (pd=1) - - 100 a cbp - 4.7 - f resr=1 ohm note: 1. it is recommended that a 10 f or higher capacitor and a 100 nf bypass capacitor are connected between vdd and the closest vss pin of the device. 2. for ensuring power stability, a 4.7 f or higher capacitor must be connected between ldo pin and the closest vss pin of the device.
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 57 of 65 revision 1.09 7.4.2 specification of low voltage reset parameter condition min. typ. max. unit quiescent current v dd =5.5 v - - 5 a temperature - -40 25 85 threshold voltage temperature=25 1. 7 2.0 2.3 v temperature= -40 - - v temperature=85 - - v hysteresis - 0 0 0 v 7.4.3 specification of brownout detector parameter condition min. typ. max. unit quiescent current av dd =5.5 v - - 1 40 a temperature - -40 25 85 brownout voltage bov_vl [1:0]=11 4. 2 4. 4 4.6 v bov_vl [1:0]=10 3. 6 3. 75 3. 9 v bov_vl [1:0]=01 2.6 2.7 2.8 v bov_vl [1:0]=00 2. 1 2. 2 2. 3 v hysteresis - 30 - 150 mv 7.4.4 specification of power - on reset (5 v) parameter condition min. typ. max. unit temperature - -40 25 85 reset voltage v+ - 2 - v quiescent current vin>reset voltage - 1 - na
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 58 of 65 revision 1.09 7.4.5 specification of usb phy usb dc electrical characteristics 7.4.5.1 symbol parameter conditions min. typ . max. unit v ih input high (driven) 2.0 v v il input low 0.8 v v di differential input sensitivity |padp - padm| 0.2 v v cm differential common - mode range includes v di range 0.8 2.5 v v se single - ended receiver threshold 0.8 2.0 v receiver hysteresis 200 mv v ol output low (driven) 0 0.3 v v oh output high (driven) 2.8 3.6 v v crs output signal cross voltage 1.3 2.0 v r pu pull - up resistor 1.425 1.575 k r pd pull - down resistor 14.25 15.75 k v trm termination voltage for upstream port pull up (rpu) 3.0 3.6 v z drv driver output resistance steady state drive* 10 c in transceiver capacitance pin to gnd 20 pf *driver output resistance doesn?t include series resistor resistance. usb full - speed driver electrical characteristics 7.4.5.2 symbol parameter conditions min. typ . max. unit t fr rise time c l =50p 4 20 ns t ff fall time c l =50p 4 20 ns t frff rise and fall time matching t frff =t fr /t ff 90 111.11 % usb power dissipation 7.4.5.3 symbol parameter conditions min. typ . max. unit i vddreg (full speed) v ddd and v ddreg supply current (steady state) standby 50 a input mode a output mode a
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 59 of 65 revision 1.09 7.5 spi dynamic c haracteristics 7.5.1 dynamic characteristics of data input and output pin symbol parameter min . typ . max . unit spi m aster m ode (vdd = 4.5 v ~ 5.5 v, 30 pf loading capacitor) t ds data setup time 16 10 - ns t dh data hold time 0 - - ns t v data output valid time - 5 8 ns spi m aster m ode (vdd = 3.0 v ~ 3.6 v, 30 pf loading capacitor) t ds data setup time 20 13 - ns t dh data hold time 0 - - ns t v data output valid time - 7 14 ns spi s lave m ode (vdd = 4.5 v ~ 5.5 v, 30 pf loading capacitor) t ds data setup time 0 - - ns t dh data hold time 2*pclk+4 - - ns t v data output valid time - 2*pclk+11 2*pclk+20 ns spi s lave m ode (vdd = 3.0 v ~ 3.6 v, 30 pf loading capacitor) t ds data setup time 0 - - ns t dh data hold time 2*pclk+8 - - ns t v data output valid time - 2*pclk+20 2*pclk+32 ns clkp=0, tx_neg=1, rx_neg=0 or clkp=1, tx_neg=0, rx_neg=1 clkp=0, tx_neg=0, rx_neg=1 or clkp=1, tx_neg=1, rx_neg=0 miso mosi data valid data valid data valid data valid spiclk miso mosi data valid data valid data valid data valid clkp=0 clkp=1 t v t ds t dh t v t ds t dh figure 7 - 2 spi master mode timing
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 60 of 65 revision 1.09 clkp=0, tx_neg=1, rx_neg=0 or clkp=1, tx_neg=0, rx_neg=1 clkp=0, tx_neg=0, rx_neg=1 or clkp=1, tx_neg=1, rx_neg=0 miso mosi data valid data valid data valid data valid spiclk miso mosi data valid data valid data valid data valid clkp=0 clkp=1 t v t ds t dh t v t ds t dh figure 7 - 3 spi slave mode timing
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 61 of 65 revision 1.09 8 package dimens i ons 8.1 64l lqfp (7 x 7 x1.4mm footprint 2.0 mm)
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 62 of 65 revision 1.09 8.2 48l lqfp (7x7x1.4mm footprint 2.0mm)
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 63 of 65 revision 1.09 8.3 3 3 l qfn ( 5 x 5x0.8 mm)
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 64 of 65 revision 1.09 9 revision h istory version date page / chap. description v 1.0 0 nov . 15, 20 10 - preliminary version i nitial i ssued v 1.01 dec. 7, 2010 chap. 3 corrected the selection guide table for qfn33. v1 .02 j an. 1 3 , 2011 chap. 5 chap. 7 1. corrected the watchdog timer clock source selection 2. corrected the electrical characteristics. v 1.0 3 march 14, 2011 chap. 3 chap. 7 chap. 8 1. add ed the lqfp 64 - pin part number for 7x7x1.4mm package. (nuc122sd2an, nuc122sc1an) 2. corrected the lqfp 64 - pin pin diagram. 3 . update d dc and ac e lectrical c haracteristics and added the spi dynamic c haracteristic s . 4 . update d lqfn 48 - pin package dimensions. v 1.0 4 march 31 , 2011 chap. 2 chap. 3 chap. 4 chap. 5 chap. 8 1. removed the lqfp 64 - pin part number for 10x10x1.4mm package. 2. replaced ?12 mhz ? with ? 4~24 mhz ? in some contents and block diagrams. v 1.05 apr.29 , 2011 chap. 1 chap. 2 chap. 3 chap. 5 chap. 7 1. updated the table of specification of ldo and power management. 2. removed the lin function from uart controller. 3. corrected the ? pwm_ crlx/ pwm_ cflx(x=0~3) ? to ?crl r x/cfl r x(x=0~3) ? in the overview of pwm generator and capture timer chapter. 4. corrected the ? 1xx ? to ?111 ? in system clock and systick clock control block diagram. 5. added the clock generator global view diagram. 6. corrected the ?rx 0/ 1 ? and ? tx 0/ 1 ? to ? rxd0/ 1 ? and ? txd 0/ 1 ? in pin configuration and pin description. v 1.0 6 may 30 , 2011 chap. 3 all 1. corrected the pin description of pins 17 and 18 for lqfp 48 - pin. 2. corrected the typo of year on the footer. v 1.0 7 june 8 , 2011 chap. 2 chap. 7 1. corrected the trimmed condition for the internal 22.1184 mhz high speed oscillator in the ? clock control ? item of feature list. 2. corrected the s pecification of the ? internal 22.1184 mhz high speed oscillator ?. v 1.0 8 june 21 , 2011 chap. 2 1. added the condition and corrected the speed of spi in master/slave mode in the ?spi ? item of feature list. v1.09 may 16, 2014 chap. 3 chap. 8 1. added the pf.2 and pf.3 function on ps2dat and ps2clk in pin diagram and pin description. 2. corrected qfn33 package dimension .
num icro ? nuc1 22 d ata s heet may 16 , 201 4 page 65 of 65 revision 1.09 important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed , ?insecure usage?. insecure usage inclu des, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, al l types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customer?s risk, and in the event that third parties lay claims to nuvoton as a result of customer?s insecure usage, customer shall indemnify the damages and liabilities thus incurred by nuvoton.

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